Parametric memory decoding as a routing comparator

Research 18 tested task-local LoRA weight editing. Research 20 tests a learned cortex controlling a frozen language organ. Research 22 asks a different question: given a fixed bank of already trained LoRAs on one shared backbone, can the query and the bank’s own parameters identify which LoRA to activate without a learned gate or retrieval index?

The project is prompted by the PMD paper (arXiv:2607.04118), which studies exactly that setting. The citation motivates a comparator; it is not evidence that Oczy already has addressable or metabolized memory. The paper’s mechanism applies directly only to a LoRA external-parametric-memory bank, not to Oczy’s non-LoRA fast/slow cortex state or the multi-model organs in Research 21.

Stage A is a standalone addressability comparator. It reproduces and stresses the PMD mechanism on a shared frozen backbone and frozen LoRA bank. It can start regardless of Research 20 and does not use cortex state. It tests routing and routed-task utility, not learning, consolidation, trace deletion, or metabolism.

Stage B is cortex integration. Only after Research 20 accepts and a valid Stage A route exists, it tests whether learned query-conditioned cortex state adds useful routing information to the already validated LoRA-bank interface. Any Stage B gain is attributed to the learned cortex path only after matched zero, swap, and shuffle interventions.

Stage A

INDEPENDENT OF R20Strict and calibrated PMD versus retrieval, learned-router, and internal-signal comparators.

Stage B

BLOCKEDRequires R20 acceptance and a valid Stage A route.

Retrieval

MANDATORY BASELINEBM25 beat PMDRouter on every PaperQA and NQ-DomainLoRA backbone in the paper; retrieval stays in every table.

Calibration

SEPARATE VERDICTA calibrated-only win is reported as calibration-dependent PMD, not strict zero-shot routing.

The instrument is versioned independently of eval/v2 and all Research 20 measuring instruments. It must not edit their episodes, scorers, thresholds, or evaluation files. Memory families, splits, LoRA validity gates, routing conditions, controls, primary metrics, and the DEV distribution and power freeze are all pre-registered.

There is no fixed accuracy threshold in the spec. Meaningful margins come from the DEV distribution check, not a paper result or desired verdict. The frozen CI procedure, multiplicity correction, bootstrap scheme, and target power are chosen before unblinding. A fallback rule labels underpowered bank tiers INCONCLUSIVE rather than pooling them post hoc.

• H-PMD-STRICT and H-PMD-CAL receive separate verdicts; a calibrated-only win does not rescue strict zero-shot.
• H-CORTEX-PMD requires matched zero, swap, and shuffle interventions on cortex state while the backbone and LoRA bank remain bit-identical.
• Neither stage is Research 21: selecting LoRAs that share a backbone does not validate routing among independently frozen language, action, vision, or code models.